Typically, each integrated circuit or chip (e.g., an integrated electronic circuit) includes a substrate of semiconductor material on which a functional region is integrated (typically, functional components and metal layers for the corresponding electrical connections) for implementing specific functionalities of the chip. The chips are formed in large number within a wafer of semiconductor material through a production process typically executed in a sequence of stages, after which the wafer includes a plurality of identical chips. Each chip also includes a respective perimeter protection ring (seal ring), which has the purpose of both mechanically strengthening the chip (especially, in order to avoid subsidence of the same during the cutting operation of the wafer for separating the various chips formed thereon) and minimizing risks of contamination and inclusion of foreign bodies within the functional region of the chip. Adjacent chips within the wafers are spaced apart from each other by separation regions called scribe lines, which typically act as cutting lines along which the chips are separated from each other by cutting operations (through a suitable saw or laser); once the chips have been separated, they are encapsulated in respective packages.
In case that the integrated circuits are found to be defective before or during their use, they are returned to the manufacturer in order to perform failure analysis; therefore, the possibility of tracing the original position of the chip within the corresponding wafer (or other significant parameters) is of strategic importance for the management of quality of the production process. In fact, performance and reliability of each chip may also vary considerably depending on its position within the corresponding wafer (or other parameters relating or having reference to the production process). For this reason, it may be important for the manufacturer to know at which level of the production process to act for improving the quality thereof.
To such purpose, in the production process of integrated circuits there are also provided marking operations of the same so as to keep track of the positions (and/or of other identification parameters) of the corresponding chips within the wafer also downstream of the corresponding production process. To this purpose, in the state of the art it is possible to identify substantially two different approaches for performing said markings and obtaining traceable chips.
In particular, a first approach provides for electrically writing significant information within suitable dedicated memory circuits (e.g., non-volatile memories) formed within each chip; however, the solutions using such approach may be affected by a relatively large waste in terms of area occupation of the chip (having to integrate also such memory circuits within the corresponding functional region), with resulting increase of the production costs of the integrated circuit. Moreover, such solutions may not be applicable to chips having a fully analogical functional region, both because of problems of compatibility of interface between the latter and the (digital) memory circuits, and because of the need of specific technological processes to make such memory circuits. Moreover, the information reading, being indirect (but requiring proper reading circuits), may be difficult and slow.
Another approach provides for making a physical marking on each chip that may be read directly and from which information about the chip may be quickly deduced.
For example, in U.S. Pat. No. 3,562,536, which is incorporated by reference, such marking includes bar codes made within the scribe lines and obtained by etching processes; however, the cutting operation along the scribe lines may damage such bar codes, thus making the information encoded by them inaccessible; moreover, typically it may be preferred to allocate the entire surface of the scribe lines to functional structures (called TEG, or Test Element Group) through which it is possible to perform parametric measurements of the production process.
Alternatively, typically the marking may be executed by forming (numeric or alphanumeric) codes or maps during the production process of the chips through proper photolithographic masks; however, such solution is may not be applicable for the current production processes. In fact, with the increase of the size of the wafers and with the increase of the capacity of integration of the integrated circuits, each step of the production process of the chips (through the corresponding photolithographic mask) may not be carried out by a single step over the entire surface of the wafer, but is typically carried out step by step on different portions of the wafer; at each step the mask acts on a corresponding area of the wafer in which, at the end of the process, a corresponding group of chips will be made (with each chip of the group having its own marking); the same operation is repeated to apply the same mask on the entire surface of the wafer. In this way, chips of different groups in the same relative position will have the same marking; as a consequence, auxiliary markings will be needed for distinguishing the different groups of chips in the wafer from each other. Moreover, such solution makes the marking within the region of the chip bounded by the respective seal ring, i.e., wherein the corresponding functional components are integrated; this may imply a significant increase of the overall area occupation of the chip, especially if the markings include codes (or maps) being long and complex and/or requiring auxiliary markings.
Another solution, disclosed in U.S. Pat. No. 6,063,685, which is incorporated by reference, provides for making the marking in regions not used (for electrical connections) of a last metal layer of the functional region of the respective chip through laser-writing techniques and equipment; however, such marking, being made within inner regions of the seal ring, does not exclude the possibility that the corresponding functional region is accidentally damaged during writing, with resulting loss of production yield of the chips; moreover, in case that the availability of such inner regions of the seal ring is not ensured for marking, this could represent a further design parameter, with consequent possible cost increases.